ABOUT
Rakesh Kanjilal is an Associate at IIT Gandhinagar under the SAMARTH Programme, working across semiconductor technology, circuit design, and engineering tools. His work brings together analog and mixed-signal systems, EDA infrastructure, automation, and practical engineering workflows connecting design, verification, and implementation.
EXPERIENCE
01Working with the SAMARTH Programme on semiconductor education, training, and related engineering activities at IIT Gandhinagar, with work centered around semiconductor technology, technical workflows, and engineering tools.
Worked on analog circuit design, layout, and verification, along with semiconductor design workflows and EDA-based engineering activities.
The work also included EDA automation, semiconductor PDK integration, Cadence environment management, tool configuration, licensing, verification workflows, and maintaining the surrounding semiconductor design ecosystem.
Supported teaching and laboratory activities in analog and mixed-signal circuit design and semiconductor device physics, including practical guidance around circuit analysis, simulation, and related engineering workflows.
Teaching and laboratory activities · IIT Gandhinagar
EDUCATION
02Kanjilal completed his Master’s degree in 2025 from the Department of Electronics and Communication Engineering, with a specialization in VLSI and Embedded Systems. During his Master’s, he volunteered to conduct laboratory classes on Analog Circuit Design, covering both circuit analysis and simulation. As part of his master’s research, he worked on the design and development of a high-speed SAR ADC (Successive Approximation Register Analog-to-Digital Converter).
Completed his Bachelor’s degree in Electronics and Communication Engineering. During his undergraduate studies, he worked on the analysis and simulation of a Capacitive Micromachined Ultrasonic Transducer (CMUT) cell. https://doi.org/10.36548/jei.2023.3.006
He completed his Diploma in Engineering from Falakata Polytechnic department of Electronics and Tele-communication Engineering
TECHNICAL SKILLS
03Transistor-level design of OTAs, amplifiers, CMFB circuits, ADCs, comparators, current mirrors, feedback loops, compensation, and power-management circuits, with extensive AC/DC, transient, corner, stability, CMRR, PSRR, and performance analysis.
Cadence Virtuoso-based IC design, PDK integration, technology-file configuration, design-environment setup, library management, and technology-specific design flows across advanced CMOS processes.
Schematic-driven analog design, transistor-level layout, physical implementation, and verification of analog circuits, including design-rule, layout-versus-schematic, parasitic-aware, and post-layout verification workflows.
Verilog and mixed-signal modeling, digital logic design, ADC architectures, synthesis and implementation workflows, Yosys, OpenLane, Sky130, RISC-V/TL-Verilog ecosystems, and open-source silicon development.
RHEL/Linux administration, engineering-server deployment, EDA software installation, PDK and library deployment, user and access management, remote-access environments, licensing infrastructure, and computational environments for semiconductor design.
Python, Bash, JavaScript, Git/GitHub, scripting, workflow automation, engineering utilities, and development of tools to streamline semiconductor design, simulation, and infrastructure workflows.
SELECTED PROJECTS
04Designed a complete transistor-level voltage-mode buck converter in Cadence Virtuoso, including the power stage, high-side PMOS/low-side NMOS switches, ramp generator, continuous-time comparator, SR latch, break-before-make (BBM) driver, two-stage error amplifier, and Type-III compensation network. Designed the feedback and compensation network for closed-loop regulation and analyzed DC gain, UGB, phase margin, load regulation, transient response, and efficiency under light- and heavy-load conditions.
Designed and characterized folded-cascode OTAs for complementary input common-mode ranges, targeting high gain, high CMRR, low power, and wide bandwidth. Performed transistor sizing and bias-current design followed by DC, AC, transient, process-corner, CMRR, output-swing, and power-consumption analysis. The high-ICMR design achieved 84.98 dB differential gain, 11.76 MHz GBW, 68.95° phase margin, and 18.52 µW power consumption at the reported operating condition.
Designed a fully differential amplifier and investigated multiple CMFB architectures, including resistive CMFB, source-follower-buffered CMFB, and an active error-amplifier-based CMFB loop. Analyzed differential gain, common-mode gain, CMRR, UGB, voltage swing, loop gain, and stability across process corners. The active CMFB architecture demonstrated a reported CMRR of 137.78 dB, with a CMFB loop gain of approximately 130 dB, while maintaining more than 45 dB differential gain across the analyzed corners.
Investigated the electro-mechanical behavior of a single-cell CMUT through 3D FEM simulations in COMSOL Multiphysics, comparing SiC and Si₃N₄ membrane materials.
RESEARCH INTERESTS
05CONTACT